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Soft Error Register File
The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. In this example, the equations for the parity bits may be expressed as: p67=ei xor e3 xor e5 xor e7 xor e9 xor e11 xor e13 p68=e2 xor e4 xor e6 New York: ACM Press, 2009, 44(7): 41–49.Google ScholarMatthew R G, Ringenberg J S, Dan Ernst, et al. Juni 20005. weblink
The SI unit of power is the watt, one joule per second. Apr. 2010ASAssignmentFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FLEISCHER, BRUCE M.;FOX, THOMAS W.;MUFF, ADAM J.;AND OTHERS;SIGNING DATES FROM 20100303 TO 20100331;REEL/FRAME:024187/0013Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y19. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer That is, an exemplary embodiment uses the hardware (i.e., in a way that is transparent to the software and operating system) and a processor instruction (i.e., an instruction in the processor
The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. morefromWikipedia Graphics processing unit A graphics processing unit or GPU (also occasionally called visual processing unit or VPU) is a specialized electronic circuit designed to rapidly manipulate and alter memory in Use of this web site signifies your agreement to the terms and conditions. It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures.
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- Piscataway N J: IEEE Press, 2005: 243–254.Google ScholarLee J, Shrivastava A.
- GPUs are used in embedded systems, mobile phones, personal computers, workstations, and game consoles.
- In an exemplary embodiment, the error detection and correction is performed by soft error recovery circuitry in a floating point processing engine.
- The error recovery circuitry 116 inserts, via the address capture circuitry 112, one or more instructions within the arithmetic pipeline 110.
Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and In an exemplary embodiment, the soft error is detected using a parity bit that detects a parity error. When the parity error is correctable, the arithmetic pipeline 110 selects whichever operand is correct, and writes the result back to a target address, in both copies of the register file BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS The subject matter that is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion
A parity bit contains no information as to the individual values of the bits it represents, but rather indicates whether there are an even or odd number of “ones” in the The system returned: (22) Invalid argument The remote host or network may be down. MiBench: A free, commercially representative embedded benchmark suite[C]// IEEE International Workshop on Workload Characterization, 2001. this morefromWikipedia Soft error In electronics and computing, a soft error is an error in a signal or datum which is wrong.
All of these tasks are completely hidden from the operating system and applications. The inserted instruction(s) read the offending register file data (e.g., a register), once from each copy (i.e., from register file 106 and register file 108), select the good version based on Aspects of the present invention are described above with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. Using register lifetime predictions to protect register files against soft errors[C]//37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2007.
VeröffentlichungsnummerUS8560924 B2PublikationstypErteilung AnmeldenummerUS 12/652,360 Veröffentlichungsdatum15. http://www.google.ch/patents/US8560924 In an exemplary embodiment, the address capture circuitry 112 is located in the arithmetic unit 102 and the address is captured during normal operation so that it is available during the Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. Part of Springer Nature.
The system of claim 1, wherein input to the detecting includes parity bits. 9. have a peek at these guys A compiler-microarchitecture hybrid approach to soft error reduction for register files[J]. The registers are individually accessible via an address or index into the register file. Mai 200718.
The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The system of claim 1, wherein the arithmetic pipeline enters a quiescent state in response to detecting the corrupted data and exits the quiescent state after the inserted error recovery instruction Soft errors are phenomena seen in electronic devices when an extraneous charge is introduced into the system, causing an incorrect value to be observed on a signal or in a storage check over here The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to
In a pipeline, the output from one stage is the input to a next stage. Okt. 2007Renesas Technology CorporationAssociative memory capable of searching for data while keeping high data reliabilityUS200801683058. J.
Jan. 199919. The control unit 104 then signals to the error recovery circuitry 116 to begin the error recovery sequence. New York: ACM Press, 2006: 421–431.Google ScholarGokhan M, Chowdhury M H, Mallik A, et al. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT;ASSIGNORS:FLEISCHER, BRUCE M.;FOX, THOMAS W.;MUFF, ADAM J.;AND OTHERS;SIGNING DATES FROM 20100326 TO 20100331;REEL/FRAME:024250/0896Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y2.
Skip to MainContent IEEE.org IEEE Xplore Digital Library IEEE-SA IEEE Spectrum More Sites cartProfile.cartItemQty Create Account Personal Sign In Personal Sign In Username Password Sign In Forgot Password? However, the original pattern of ones and zeros cannot be reconstructed purely from this knowledge alone. Jan. 200731. http://unordic.com/soft-error/soft-error-mitigation.html März 2009International Business Machines CorporationSoft error handling in microprocessorsUS7865729 *2.
Once the good data is safely written to both copies of the register file, the error recovery circuitry 116 signals to the control unit 104 that the recovery sequence is complete. A system for performing soft error recovery, the system comprising: a first register file; a second register file mirroring the first register file; an arithmetic pipeline for receiving data read from The arithmetic unit 102 includes register file 106 and register file 108, as well as an arithmetic pipeline 110.