(Solved) Soft Error Rates In Deep-submicron Cmos Technologies Tutorial

Home > Soft Error > Soft Error Rates In Deep-submicron Cmos Technologies

Soft Error Rates In Deep-submicron Cmos Technologies

Soft-errors induced by terrestrial neutrons and natural alpha-particle emitters in advanced memory circuits at ground level. Single-event transient pulse quenching in advanced CMOS logic circuits. HBD using cascode-voltage switch logic gates for SET tolerant digital designs. In addition, the SE induced coupling delay effect has been studied and compared to radiation induced soft delay effect for various technologies. check over here

IEEE T Nuc Sci, 2012, 59: 1040–1047CrossRefGoogle Scholar90.Loveless T D, Kauppila J S, Jagannathan S, et al. Naseer, J. Seifert, & M. IEEE Transactions on Nuclear Science, 53(6), 3306–3311.CrossRefGoogle Scholar16.Balasubramanian, A., Amusan, O. http://ieeexplore.ieee.org/iel5/6669/17838/00824159.pdf

The Community for Technology Leaders Toggle navigation Libraries & Institutions About Resources RSS Feeds Newsletter Terms of Use Peer Review Subscribe LOGIN CSDL Home E ETS 2006 TABLE OF CONTENTS Institutional Sign In By Topic Aerospace Bioengineering Communication, Networking & Broadcasting Components, Circuits, Devices & Systems Computing & Processing Engineered Materials, Dielectrics & Plasmas Engineering Profession Fields, Waves & Electromagnetics General IEEE T Nuc Sci, 2011, 58: 2719–2725CrossRefGoogle Scholar66.Mavis D G, Eaton P H. L. (2000).

China Technol. Dekker, F. In comparisons, the distributed nature of interconnects has been taken into account and results are demonstrated using HSPICE simulations with interconnect and device parameters derived in 130, 90 and 65 nm technologies.KeywordsSingle Sci. (2014) 57: 1846.

Impact of heavy ion energy and nuclear interactions on single-event upset and latchup in integrated circuits. http://www.eas.asu.edu/~ptm. Fukuma 1987 Electrical modelling of LSCRs in deep submicron CMOS technologies for circuit-level simulation of ESD protection structures Authors: Caillard, Azais, Nouet, Dournelle, Salome 2003 Circuit design techniques for deep submicron http://opensample.info/soft-error-rates-in-deep-submicron-cmos-technologies On-chip measurement of single-event transients in a 45 nm silicon-on-insulator technology.

Your cache administrator is webmaster. Measurement and analysis of interconnect crosstalk due to single events in a 90 nm CMOS technology. Threshold energy of neutron-induced single event upset as a critical factor. IEEE T Nuc Sci, 2009, 56: 3085–3092CrossRefGoogle Scholar18.Barak J, Levinson J, Victoria M, et al.

  1. Impact of logic synthesis on soft error vulnerability using a 90-nm bulk CMOS digital cell library.
  2. Radiation characterization of a radiation hardened low voltage differential signaling (LVDS) driver and receiver.
  3. IEEE T Nuc Sci, 2004, 51: 3278–3284CrossRefGoogle Scholar13.Gasiot G, Giot D, Roche P.
  4. In: Proceedings of the IEEE International Reliability Physics Symposium.

In-place FPGA retiming for mitigation of variational single-event transient faults. http://link.springer.com/article/10.1007/s10470-013-0216-6 In Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (pp. 597–604).34.Maheshwari, A., Burleson, W., & Tessier, R. (2004). IEEE T Nuc Sci, 2007, 54: 2338–2346CrossRefGoogle Scholar6.Autran J L, Munteanu D, Roche P, et al. Piscataway: IEEE, 2008. 222–225Google Scholar58.Uemura T, Tanabe R, Matusyama H.

Shivakumar, M. http://unordic.com/soft-error/soft-error-mitigation.html IEEE T Nuc Sci, 2008, 55: 2842–2853CrossRefGoogle Scholar69.Ferlet-Cavrois V, Kobayashi D, Mcmorrow D, et al. Single-event charge collection and upset in 40-nm dual- and triple-well bulk CMOS SRAMs. We also review the hardening strategies for different types of soft errors from different perspective and present the challenges in testing, modeling and hardening assurance of soft error issues we have

F., Bhuva, B., Alles, M., Massengill, L. The susceptibility of 45 and 32 nm bulk CMOS latches to low-energy protons. Generated Fri, 28 Oct 2016 01:19:44 GMT by s_wx1194 (squid/3.5.20) ERROR The requested URL could not be retrieved The following error was encountered while trying to retrieve the URL: Connection this content Fast SEU detection and correction in LUT configuration bits of SRAM-based FPGAs.

Also, a lower power supply voltage leads to a smaller Qcrit. Angular dependence of single event sensitivity in hardened flip/flop designs. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM cells with parametric sensitivity.

Operational SER calculations on the SAC-C orbit using the multi-scales single event phenomena predictive platform (MUSCA SEP3).

Koren., & W.Burleson. (2003). Heavy Ion, high-energy, and low-energy proton SEE sensitivity of 90-nm RHBD SRAMs. In this paper, we review the evolution of two main aspects of soft error-SEU and SET, including the new mechanisms to induced SEUs, the advances of the MCUs and some newly IEEE Transactions on Reliability, 53(3), 342–348.CrossRefGoogle Scholar22.Sayil, S., Boorla, V.

IEEE T Dev Mat Rel, 2011, 11: 551–554CrossRefGoogle ScholarCopyright information© Science China Press and Springer-Verlag Berlin Heidelberg 2014Authors and AffiliationsDu Tang1ChaoHui He1Email authorYongHong Li1Hang Zang1Cen Xiong1JinXin Zhang11.School of Nuclear Science and TechnologyXi’an Jiaotong UniversityXi’anChina About this article Print ISSN D., & Normand, E. (2004). Piscataway: IEEE, 2012. 115–120Google Scholar55.Ernst D, Nam S K, Das S, et al. have a peek at these guys Production and propagation of single-event transients in high-speed digital logic ICs.

IEEE T Nuc Sci, 2005, 52: 2510–2515CrossRefGoogle Scholar83.Quming Z, Choudhury M R, Mohanram K. Proton upsets in orbit. IEEE T Nuc Sci, 2008, 55: 3394–3400CrossRefGoogle Scholar2.Sierawski B D, Mendenhall M H, Reed R A, et al.