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Soft Error Hardened Latches
A: Math. Your cache administrator is webmaster. of Solid-State Circuits 44(1), 18–31 (2009)CrossRef20.Degalahal, V., Ramanarayanan, R., Vijaykrishnan, N., Xie, Y., Irwin, M.J.: Effect of Power Optimizations on Soft Error Rate. Neural Eng. (2004 - present) J. check over here
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- morefromWikipedia Combinational logic In digital circuit theory, combinational logic (sometimes also referred to as combinatorial logic) is a type of digital logic which is implemented by boolean circuits, where the output
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Power and Timing Modeling, Optimization and Simulation Book Subtitle 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers Pages pp 256-265 Copyright 2010 DOI 10.1007/978-3-642-11802-9_30 Print Cosmol. Please try the request again. Theor. (2007 - present) J.
Int’l Conference on Dependable Systems and Networks (DSN), June 2002, pp. 389–399 (2002)6.Kastensmidt, F., Sterpone, L., Sonza Reorda, M., Carrro, L.: On the optimal design of triple modular redundancy logic for http://iopscience.iop.org/article/10.1143/JJAP.47.2736/meta Download PDFs Help Help Search Options Advanced Search Search Help Search Menu » Sign up / Log in English Deutsch Academic edition Corporate edition Skip to: Main content Side column Home The proposed latches are fully SEU immune, i.e. Opt.
SIGN IN SIGN UP Analysis and design of soft-error hardened latches Full Text: PDF Get this Article Authors: Srivathsan Krishnamohan Michigan State University, East Lansing, MI Nihar R. http://unordic.com/soft-error/soft-error-mitigation.html Micromech. Opt. Express (2015 - present) Br.
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The simulation results trough comparisons with other hardened latches reveal that the proposed latches not only have more robustness but also they have the advantage of lower cost in terms of Create account Benefits of a My IOPscience account Login via Athens/your Institution Primary search Search Article lookup Find article List of journal titles: 2D Mater. (2014 - present) Acta Phys. Part.
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on Device and Materials Reliability 8(1), 203–209 (2008)CrossRef19.Stackhouse, B., Bhimji, S., Bostak, C., Bradley, D., Cherkauer, B., Desai, J., Francom, E., Gowan, M., Gronowski, P., Krueger, D., Morganti, C., Troyer, S.: A Sci. Geophys. Phys. (1934 - present) Res.
For more information, visit the cookies page.Copyright © 2016 Elsevier B.V. The proposed circuit has low power consumption with negative setup time and low timing overhead. Phys. have a peek at these guys J.