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Soft Error Hardened Latch

Sci. Int’l Conference on Dependable Systems and Networks (DSN), June 2002, pp. 389–399 (2002)6.Kastensmidt, F., Sterpone, L., Sonza Reorda, M., Carrro, L.: On the optimal design of triple modular redundancy logic for Chem. Moreover, they can mask Single Event Transients (SETs) occurring in combinational logics and reaching the input of the latches. check over here

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Errors may be caused by a defect, usually understood either to be a mistake in design or construction, or a broken component. J. Phys. (1988 - present) J.

  1. morefromWikipedia Moore's law Moore's law is a rule of thumb in the history of computing hardware whereby the number of transistors that can be placed inexpensively on an integrated circuit doubles
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  5. morefromWikipedia Electrical network An electrical network is an interconnection of electrical elements such as resistors, inductors, capacitors, transmission lines, voltage sources, current sources and switches.

Nucl. Disc. (2008 - 2015) Converg. Math. (1995 - present) J. Meas. (1980 - 1992) Commun.

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Opt. Phys. IEEE Journal of Solid-State Circuits 39(9), 1536–1543 (2004)CrossRef11.Sasaki, Y., Namba, K., Ito, H.: Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger. Technol. (2015 - present) Quantum Semiclass.

morefromWikipedia Tools and Resources Buy this Article Recommend the ACM DLto your organization Request Permissions TOC Service: Email RSS Save to Binder Export Formats: BibTeX EndNote ACMRef Upcoming Conference: GLSVLSI '17 Neural Eng. (2004 - present) J. That is, sequential logic has state (memory) while combinational logic does not. Soc.

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In: Workshop on System Effects of Logic Soft Errors (2005)14.Das, S., Tokunaga, C., Pant, S., Ma, W.-H., Kalaiselvan, S., Lai, K., Bull, D.M., Blaauw, D.T.: RazorII: In Situ Error Detection and Biol. (1956 - present) Phys. USSR Izv. (1967 - 1992) Math. have a peek at these guys Mol.

IEEE J. Phys. Phys. (1975 - 1988) J. Test Conference, November 2005, pp. 687–696 (2005)3.Omana, M., Rossi, D., Metra, C.: Latch susceptibility to transient faults and new hardening approach.

The system returned: (22) Invalid argument The remote host or network may be down. View full text Microelectronics ReliabilityVolume 53, Issue 6, June 2013, Pages 912–924 Low cost soft error hardened latch designs for nano-scale CMOS technology in presence of process variationRamin Rajaeia, A soft error is also a signal or datum which is wrong, but is not assumed to imply such a mistake or breakage.